1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of patterning features in a structure such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate using a multiple sidewall image transfer technique.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Device designers have been very successful in improving the electrical performance capabilities of transistor devices, primarily by reducing the size of or “scaling” various components of the transistor, such as the gate length of the transistors. In fact, device dimension on modern day transistors have been reduced to the point where direct patterning of such features is very difficult using existing 193 nm based photolithography tools and technology. Thus, device designers have employed various techniques to pattern very small features. On such technique is generally known as a sidewall image transfer technique.
FIGS. 1A-1E depict one illustrative example of a prior art sidewall image transfer technique. As shown in FIG. 1A, a mandrel 12 is formed above a structure 10, such as a semiconducting substrate. The mandrel 12 may be made of a variety of materials, e.g., amorphous silicon, polysilicon, etc. The size of the mandrel 12 may vary depending upon the particular applications. The mandrel 12 may be formed be depositing and patterning a layer of mandrel material using known deposition, photolithography and etching tools and techniques. Next as shown in FIG. 1B, a layer of spacer material 14 is conformably deposited above the mandrel 12 and the structure 10. The layer of spacer material 14 may be comprised of a variety of materials such as, for example, silicon nitride, silicon dioxide, etc. As reflected in FIG. 1C, an anisotropic etching process is performed to define spacers 14A adjacent the mandrel 12. Then as shown in FIG. 1D, the mandrel 12 is removed by performing a selective etching process that leaves the spacers 14A to act as masks in a subsequent etching process that defines feature 18 in the structure 10, as depicted in FIG. 1E.
The present disclosure is directed to various methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique.